7

Remove input power before changing the output voltage.

Adjusting the output voltage during operation could toggle

the PGOOD signal and exercise the overvoltage protection.

All VID pin combinations resulting in a 0V output setting

activate the Power-On Reset function and disable the gate

drive circuitry. For these specific VID combinations, though,

PGOOD asserts a high level. This unusual behavior has

been implemented in order to allow for operation in dual-

microprocessor systems by AND-ing the PGOOD signals

from the two individual power converters.

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very

important. Switching current from one power device to another

can generate voltage transients across the impedances of the

interconnecting bond wires and circuit traces. These

interconnecting impedances should be minimized by using

wide, short printed circuit traces. The critical components

should be located as close together as possible, using ground

plane construction or single point grounding.

Figure 5 shows the critical power components of the

converter. To minimize the voltage overshoot the

interconnecting wires indicated by heavy lines should be

part of ground or power plane in a printed circuit board. The

components shown in Figure 5 should be located as close

source connections from the HIP6014 must be sized to

handle up to 1A peak current.

Figure 6 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

close to the SS pin because the internal current source is

only 10

to the BOOT and PHASE pins.

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

oscillator (OSC) triangular wave to provide a pulse-width

PHASE node. The PWM wave is smoothed by the output filter

PGND

LGATE

UGATE

PHASE

RETURN

HIP6014

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

+12V

HIP6014

SS

GND

BOOT

PHASE

FIGURE 7. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

REFERENCE

ESR

OSC

ERROR

AMP

PWM

DRIVER

(PARASITIC)

+

-

DACOUT

COMP

FB

HIP6014

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

+

-

+

-

OSC

HIP6014