2-293

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

response time to the removal of load. Be sure to check both

of these equations at the minimum and maximum output

levels for the worst case response time.

Input Capacitor Selection

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select bulk input capacitors with voltage and

current ratings above the maximum input voltage and largest

RMS current required by the circuit. The capacitor voltage

rating should be at least 1.25 times greater than the

maximum input voltage. The RMS current rating requirement

for the input capacitors of a buck regulator is approximately

1/2 of the summation of the DC output load current.

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use ceramic capacitance

for the high frequency decoupling and bulk capacitors to

supply the RMS current. Small ceramic capacitors can be

placed very close to the upper MOSFET to suppress the

voltage induced in the parasitic circuit impedances.

For a through-hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo

MV-GX or equivalent) may be needed. For surface mount

designs, solid tantalum capacitors can be used, but caution

must be exercised with regard to the capacitor surge current

rating. These capacitors must be capable of handling the

surge current at power-up. The TPS series available from

AVX, and the 593D series from Sprague are both surge

current tested.

MOSFET Selection/Considerations

The HIP6020 requires 5 external transistors. Three

N-channel MOSFETs are employed by the PWM converters.

The GTL and memory linear controllers can each drive a

MOSFET or a NPN bipolar as a pass transistor. All these

gain, saturation voltages, gate supply requirements, and

thermal management considerations.

PWM1 MOSFET Selection and Considerations

In high-current PWM applications, the MOSFET power

dissipation, package selection and heatsink are the dominant

design factors. The power dissipation includes two loss

components; conduction loss and switching loss. These losses

are distributed between the upper and lower MOSFETs

according to the duty factor. The conduction losses are the

main component of power dissipation for the lower MOSFETs.

Only the upper MOSFET has significant switching losses, since

the lower device turns on and off into near zero voltage.

The equations presented assume linear voltage-current

transitions and do not model power loss due to the reverse

recovery of the lower MOSFET’s body diode. The gate

charge losses are dissipated by the HIP6020 and don't heat

the MOSFETs. However, large gate-charge increases the

switching losses. Ensure that both MOSFETs are within their

maximum junction temperature at high ambient temperature

by calculating the temperature rise according to package

thermal resistance specifications. A separate heatsink may

be necessary depending upon MOSFET power, package

type, ambient temperature and air flow.

the same device is used for both. This is because the gate

drive applied to the upper MOSFET is different than the

lower MOSFET. Figure 13 shows the gate drive where the

upper MOSFET’s gate-to-source voltage is approximately

for the bias, the gate-to-source voltage of Q1 is 7V. The lower

gate drive voltage is +12VDC. A logic-level MOSFET is a

good choice for Q1 and a logic-level MOSFET can be used for

Q2 if its absolute gate-to-source voltage rating exceeds the

Rectifier CR1 is a clamp that catches the negative inductor

swing during the dead time between the turn off of the lower

MOSFET and the turn on of the upper MOSFET. The diode

must be a Schottky type to prevent the lossy parasitic

MOSFET body diode from conducting. It is acceptable to omit

the diode and let the body diode of the lower MOSFET clamp

the negative inductor swing, but efficiency could drop, in some

t

RISE

L

O

I

TRAN

×

V

IN

V

OUT

–

--------------------------------

=

t

FALL

L

O

I

TRAN

×

V

OUT

-------------------------------

=

P

UPPER

I

O

2

r

DS ON

()

×

V

OUT

×

V

IN

------------------------------------------------------------

I

O

V

IN

×

t

SW

×

F

S

×

2

----------------------------------------------------

+

=

P

LOWER

I

O

2

r

DS ON

()

×

V

IN

V

OUT

–

()

×

V

IN

---------------------------------------------------------------------------------

=

+12V

PGND

HIP6020

GND

LGATE

UGATE

PHASE

VCC

+5V OR LESS

NOTE:

NOTE:

Q1

Q2

+

-

CR1

HIP6020