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ADG793G Datasheet(PDF) 19 Page - Analog Devices |
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ADG793G Datasheet(HTML) 19 Page - Analog Devices |
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19 / 24 page  ADG793A/ADG793G Rev. 0 | Page 19 of 24 LDSW BIT The LDSW bit allows the user to control the way the device executes the commands loaded during the write operations. The ADG793A/ADG793G execute all the commands loaded between two successive write operations that have set the LDSW bit high. Setting the LDSW high for every write cycle ensures that the device executes the command right after the LDSW bit was loaded into the device. This setting can be used when the desired configuration can be achieved by sending a single command or when the switches and/or GPO pin are not required to be updated at the same time. When the desired configuration requires multiple commands with simultaneous updates, the LDSW bit should be set low while loading the commands, except the last one when the LDSW bit should be set high. Once the last command with LDSW = high is loaded, the device executes all commands received since the last update simultaneously. POWER ON/SOFTWARE RESET The ADG793A/ADG793G have a software reset function implemented by the RESETB bit from the second data byte loaded into the device during a write operation. For normal operation of the multiplexers and GPO pins, this bit should be set high. When RESETB = low or after power-up, the switches from all multiplexers are turned off (open) and the GPO pins are set low. READ OPERATION When reading data back from the ADG793A/ADG793G, the user must begin with an address byte and R/W bit. The switch then acknowledges that it is prepared to transmit data by pulling SDA low. Following this acknowledgement, the ADG793A/ADG793G transmit two bytes on the next clock edges. These bytes contain the status of the switches, and each byte is followed by an acknowledge bit. A logic high bit represents a switch in the on (close) state while a low represents a switch in the off (open) state. For the GPO pin (ADG793G only), the bit represents the logic value of the pin. Figure 32 illustrates the entire read sequence. The bit maps accompanying Figure 32 show the relationship between the elements of the ADG793A and ADG793G (that it, the switches and GPO pins) and the bits that represent their status after a completed read operation. Bit Map for the ADG793A RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 S1A-D1 S1B-D1 S1C-D1 - S2A-D2 S2B-D2 S2C-D2 - S3A-D3 S3B-D3 S3C-D3 - - - - - Bit Map for the ADG793G RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 S1A-D1 S1B-D1 S1C-D1 - S2A-D2 S2B-D2 S2C-D2 - S3A-D3 S3B-D3 S3C-D3 - GPO1 GPO2 - - Read Operation SCL SDA A2 A1 A0 RB14 RB15 R/W RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 START CONDITION BY MASTER STOP CONDITION BY MASTER ADDRESS BYTE ACKNOWLEDGE BY SWITCH ACKNOWLEDGE BY SWITCH ACKNOWLEDGE BY SWITCH Figure 32. ADG793A/ADG793G Read Operation |
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