W632GG8KB datasheet(13/159 Pages) WINBOND

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W632GG8KB

Publication Release Date: Jul. 28, 2014

Revision: A04

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4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET# is

asserted. Further, the SDRAM keeps its on-die termination in high impedance state after RESET#

deassertion until CKE is registered HIGH. The ODT input signal may be in undefined state until tIS

before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal may be

statically held at either LOW or HIGH. If Rtt_Nom is to be enabled in MR1, the ODT input signal

must be statically held LOW. In all cases, the ODT input signal remains static until the power up

initialization sequence is finished, including the expiration of tDLLK and tZQinit.

5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the

first MRS command to load mode register. (tXPR=max (tXS ; 5 * tCK)

6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2,

provide “Low” to BA0 and BA2, “High” to BA1.)

7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3,

provide “Low” to BA2, “High” to BA0 and BA1.)

8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue

“DLL

Enable

” command, provide “Low” to A0, “High” to BA0 and “Low” to BA1-BA2).

Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL

reset command, provide

“High” to A8 and “Low” to BA0-2).

10.Issue ZQCL command to starting ZQ calibration.

11.Wait for both tDLLK and tZQinit completed.

12.The DDR3 SDRAM is now ready for normal operation.

TIME BREAK

DON'T CARE

CK, CK#

VDD, VDDQ

RESET#

Command

ODT

RTT

tCKSRX

T = 200 µs

T = 500 µs

tDLLK

VALID

Static LOW in case Rtt_Nom is enabled at time Tg, Otherwise static HIGH or LOW

ZQCL

MRS

MR2

MR3

MR1

MR0

tIS

tXPR

tMRD

tMOD

tZQinit

Tmin

CKE

10 ns

Note:

From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands.

Figure 1

– Reset and Initialization Sequence at Power-on Ramping

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