EN29GL064ATB datasheet(13/58 Pages) EON

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This Data Sheet may be revised by subsequent versions

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or modifications due to changes in technical specifications.

EN29GL064AT/B

Rev. C, Issue Date: 2011/12/01

USER MODE DEFINITIONS

Word / Byte Configuration

The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If

the

BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0-DQ15 are active and controlled by

CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0-DQ7

are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15

pin is used as an input for the LSB (A-1) address function.

Read

All memories require access time to output array data. In a read operation, data is read from one

memory location at a time. Addresses are presented to the device in random order, and the

propagation delay through the device causes the data on its outputs to arrive with the address on its

inputs.

The device defaults to reading array data after device power-up or hardware reset. To read data from

the memory array, the system must first assert a valid address on A21-A0, while driving OE# and CE#

to VIL. WE# must remain at VIH. All addresses are latched on the falling edge of CE#. Data will appear

on DQ15-DQ0 after address access time (tACC), which is equal to the delay from stable addresses to

valid output data.The OE# signal must be driven to VIL. Data is output on DQ15-DQ0 pins after the

access time (tOE) has elapsed from the falling edge of OE#, assuming the tACC access time has been

meet.

Page Read Mode

The device is capable of fast page mode read and is compatible with the page mode Mask ROM read

operation. This mode provides faster read access speed for random locations within a page. The page

size of the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits

A21-A3. Address bits A2-A0 in word mode (A2 to A-1 in byte mode) determine the specific word within

a page. The microprocessor supplies the specific word location.

The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as

long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC.

When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE.

Fast page mode accesses are obtained by keeping the “read-page addresses” constant and changing

the “intra-read page” addresses.

Autoselect

The Autoselect mode provides manufacturer ID, Device identification, and sector protection information,

through identifier codes output from the internal register (separate from the memory array) on DQ7-

DQ0.

The device only support to use autoselect command to access autoselect codes. It does not support to

apply VID on address pin A9.

• The Autoselect command sequence may be written to an address within a sector that is either in the

read or erase-suspend-read mode.

• The Autoselect command may not be written while the device is actively programming or erasing.

• The system must write the reset command to return to the read mode (or erase-suspend-read mode

if the sector was previously in Erase Suspend).

• When verifying sector protection, the sector address must appear on the appropriate highest order

address bits. The remaining address bits are don't care and then read the corresponding identifier

code on DQ15-DQ0.

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