R5F36506NFA datasheet(85/115 Pages) RENESAS

85 / 115 page

R01DS0031EJ0210 Rev.2.10

Page 85 of 111

Jul 31, 2012

M16C/65 Group

5. Electrical Characteristics

VCC1 = VCC2 = 5 V

Switching Characteristics

(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.2.4.5

In Wait State Setting 2

φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When

Inserting 1 to 3 Recovery Cycles and Accessing External Area

Notes:

Calculated according to the BCLK frequency as follows:

This standard value shows the timing when the output is off, and does not

show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up (pull-down)

resistance value.

Hold time of data bus is expressed in

t =

−CR × ln(1−V

OL/VCC2)

by a circuit of the right figure.

For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output

low level is

t =

−30 pF × 1 kΩ × In(1 − 0.2V

CC2/VCC2)

= 6.7 ns.

Calculated according to the BCLK frequency as follows:

Table 5.42

Memory Expansion and Microprocessor Modes (in Wait State Setting 2

φ + 3φ, 2φ + 4φ,

φ + 4φ, and 4φ + 5φ, and When Inserting 1 to 3 Recovery Cycles and Accessing

External Area)

Symbol

Parameter

Measuring

Condition

Standard

Unit

Min.

Max.

td(BCLK-AD)

Address output delay time

See

Figure 5.14

th(BCLK-AD)

Address output hold time (in relation to BCLK)

0ns

th(RD-AD)

Address output hold time (in relation to RD)

(Note 4)

th(WR-AD)

Address output hold time (in relation to WR)

(Note 2)

td(BCLK-CS)

Chip select output delay time

th(BCLK-CS)

Chip select output hold time (in relation to BCLK)

0ns

td(BCLK-ALE)

ALE signal output delay time

th(BCLK-ALE)

ALE signal output hold time

-4

td(BCLK-RD)

RD signal output delay time

th(BCLK-RD)

RD signal output hold time

0ns

td(BCLK-WR)

WR signal output delay time

th(BCLK-WR)

WR signal output hold time

0ns

td(BCLK-DB)

Data output delay time (in relation to BCLK)

th(BCLK-DB)

Data output hold time (in relation to BCLK) (3)

0ns

td(DB-WR)

Data output delay time (in relation to WR)

(Note 1)

th(WR-DB)

Data output hold time (in relation to WR) (3)

(Note 2)

BCLK

()

------------------40 ns

[]

–

n is 3 for 2

φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.

BCLK

()

-------------------10 ns

[]

–

m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and

3 when 3 recovery cycles are inserted.

DBi

BCLK

()

-------------------0 ns

[]

m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and

3 when 3 recovery cycles are inserted.

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