ACE732E

6V/3.5A, Fast Response, Step-Down Converter

VER 1.2

7

thermal-overload event, the l soft-start circuitry slowly ramps up current available at SW.

UVLO and Thermal Shutdown

If IN drops below UVLO threshold, the UVLO circuit inhibits switching.

Once IN rises above ULVO

threshold, the UVLO clears, and the soft-start sequence activates. Thermal-overload protection limits total

power dissipation in the device. When the junction temperature exceeds TJ=+155°C, a thermal sensor

forces the device into shutdown, allowing the die to cool. The thermal sensor turns the device on again after

the junction temperature cools by 15°C, resulting in a pulsed output during continuous overload conditions.

Following a thermal-shutdown condition, the soft-start sequence begins.

Design Procedure

Setting Output Voltages

Output voltages are set by external resistors. The FB threshold is 0.45V.

Inductor Selection

The peak-to-peak ripple is limited to 30% of the maximum output current. This places the peak current far

enough from the minimum overcurrent trip level to ensure reliable operation while providing enough current

ripples for the current mode converter to operate stably.

Output Capacitor Selection

The output capacitor keeps output ripple small and ensures control-loop stability. The output capacitor must

also have low impedance at the switching frequency. Ceramic, or a MLCC capacitors are suitable, with

ceramic exhibiting the lowest ESR and high-frequency impedance. Output ripple with a ceramic output

capacitor is approximately as follows:

[1 / (2π x f

If the capacitor has significant ESR, the output ripple component due to capacitor ESR is as follows:

Input Capacitor Selection

The input capacitor in a DC-to-DC converter reduces current peaks drawn from the battery or other input

power source and reduces switching noise in the controller. The impedance of the input capacitor at the

switching frequency should be less than that of the input source so high-frequency switching currents do not

pass through the input source. The output capacitor keeps output ripple small and ensures control-loop

stability.

PCB LAYOUT

The ACE732E employs a sophisticated control scheme to achieve the fast response and other superior

performances. So the PCB layout is recommended to strictly follow the proposed way shown below. The Cin

(22uF) and Cout (22uF or 10uF x 2) are always to be placed closest to ACE732E. The Cin1 (10nF) is also

require to be connected to AGND (not PGND) to filter out the switching noise. Please don’t short Pin2

(PGND) and Pin3 (AGND) directly, but through a PCB trace, as what’s shown below.

Please contact

ACE engineers for confirmation if one needs to change the PCB layout.