AN4124 datasheet(25/32 Pages) STMICROELECTRONICS

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AN4124

Redundancy and functions

Doc ID 023294 Rev 2

25/32

switch (Reg_Selection){

case 0 : FCCU.NCFE0.R &= (uint32_t) ~(NCFE_En << (NCFE_number%32));

/* Disable the non-critical fault */

break;

case 1 : FCCU.NCFE1.R &= (uint32_t) ~(NCFE_En << (NCFE_number%32));

/* Disable the non-critical fault */

break;

case 2 : FCCU.NCFE2.R &= (uint32_t) ~(NCFE_En << (NCFE_number%32));

/* Disable the non-critical fault */

break;

case 3 : FCCU.NCFE3.R &= (uint32_t) ~(NCFE_En << (NCFE_number%32));

/* Disable the non-critical fault */

break;

default: FCCU.NCFE3.R &= (uint32_t) ~(NCFE_En << (NCFE_number%32));

/* Disable the non-critical fault */

break;

}

};

return(exit_value);

}

A.2.10

NCF - normal to alarm - read state

uint32_t FCCU_NAFS_Read(uint32_t* NAFS_Value){

uint32_t exit_value= 0; /* Returned value = ERROR */

FCCU.CTRL.B.OPR = CTRL_OPR4;

/* Set the OP4 */

while(FCCU.CTRL.B.OPS != CTRL_OPS3); /* wait for the completion of the

operation */

*NAFS_Value = FCCU.NAFS.R; /* Read the NAFS latched state */

exit_value = 1;

/* Returned value = SUCCESS */

return(exit_value);

}

A.2.11

NCF - normal to alarm - clear state

uint32_t FCCU_NAFS_Clear(void){

uint32_t exit_value= 0; /* Returned value = ERROR */

FCCU.CTRL.B.OPR = CTRL_OPR13;

/* Set the OP13 */

while(FCCU.CTRL.B.OPS != CTRL_OPS3); /* wait for the completion of the

operation */

exit_value = 1;

/* Returned value = SUCCESS */

return(exit_value);

}

A.2.12

IRQ status

uint32_t FCCU_IRQ_Status(uint32_t CFG_TO_STAT, uint32_t* ALRM_STAT,

uint32_t* NMI_STAT){

uint32_t exit_value= 0; /* Returned value = ERROR */

if (CFG_TO_STAT == 1){

FCCU.IRQ_STAT.B.CFG_TO_STAT |= 1;/* Clear the Configuration

Time Out Error */

}else{

FCCU.IRQ_STAT.B.CFG_TO_STAT &= ~(1);/* No effect on bit */

}

*ALRM_STAT = FCCU.IRQ_STAT.B.ALRM_STAT;/* Read Alarm Interrupt Status */

*NMI_STAT = FCCU.IRQ_STAT.B.NMI_STAT;/* Read NMI Interrupt Status */

AN4124 Datasheet(PDF) 25 Page - STMicroelectronics

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