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AN4276 Datasheet(PDF) 5 Page - STMicroelectronics |
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AN4276 Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 21 page ![]() DocID024408 Rev 2 5/21 AN4276 ECC overview 1 ECC overview Error correction codes, ECC, are known techniques to protect data information against single or multiple bit errors. SRAM memories represent main field of ECC usage, where soft induced bit flips errors are common and where these problems increase with processes going to submicron ranges. ECC protection is one of the highly recommended measures of memory protection in high reliable and safety systems. There are several conventional algorithms used for ECC protection, single-error-correcting (SEC) Hamming code, single-error-correcting-double-error-detecting (SEC-DED) modified Hamming, or SEC-DED Hsiao code. All of these algorithms are based on principle of extending information bits with so called check bits in a way that bit error on reception is identified and corrected in case of one bit error or detected in case of two errors. 1.1 ECC principle Set of information symbols (data), where any bit error in one symbol leads to another valid, but wrong symbol, is transformed to another set of code words by extending information bits with check bits. The size of new code set is higher than the size of original one. It gives an option to map original information symbols to code words with specific characteristic like Hamming distance specifying number of bits in which these code words differ. 1.2 Number of check bits There is a minimum number of check bits that are needed for SEC-DED protection. Table 1 shows relations between data width and number of check bits. Table 1. SEC-DED code - number of check bits needed Data width Number of check bits 16 6 32 7 64 8 |
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