AN3018

Self tests for SPC564Ax core subsystem

Doc ID 16081 Rev 2

13/24

ECC, most notably the RAM. This capability is provided for two purposes:

–

It provides a software controlled mechanism for “injecting” errors into the

memories during data writes to verify the integrity of the ECC logic

–

It provides a mechanism to allow testing of the software service routines

associated with memory error logging

Result: after writing data with an erroneous ECC, the procedure involves reading back the

data and checking for error detection with the right parameters (single error, double error,

address of error).

Resource availability: once the RAM locations with erroneous content have been written,

the RAM is available for the application.

3.2.3

RAM address decoder

Principle: a specific test to check the RAM decoder can be implemented by inserting, at

several places in the RAM address space, data with known content. A signature using the

CRC unit of SPC564Ax can be computed by reading the RAM content at those places and

writing them in the CRC unit. The CRC can be seeded to any value by initializing the CRC

before the test.

Result: once the test is completed, the signature in the CRC unit can be compared with the

reference signature.

Resource availability: the RAM module is available during this test.

There is no restriction on the number of times the test can be performed.

3.2.4

eTPU code RAM

Principle: compute a signature over the eTPU code RAM during run time. Once enabled

(bits SCMMISEN=1 and bit VIS=0 in EPUTMCR register), this check is performed

continuously.

Result: the computed signature is automatically compared with a predefined signature in

EPTUMISCCMPR register. In case of mismatch, eTPU can also assert a global exception

interrupt indicating a global illegal state.

Resource availability: the eTPU code RAM is available during this test.

3.3

CPU parallel signature unit tests

The cores of SPC563Mx and of SPC564Ax devices have integrated signature registers to

enhance capabilities to develop core self tests.

To support applications requiring system integrity checking during operation, the Zen core

provides a parallel signature unit, which is capable of monitoring the CPU data read and

data write AHB buses, and accumulating a pair of 32-bit MISR signatures of the data values

transferred over these buses.