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AN2159 Datasheet(PDF) 11 Page - STMicroelectronics |
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AN2159 Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 23 page ![]() AN2159 SPI operations Doc ID 11400 Rev 3 11/23 t1 → t2: Latching phase. Interval value > 2 / fCLK t2 → t3: Data latched, SPI idle. Interval value > 30 ns t3 → t4: Enable SPI for read operation. Interval value > 30 ns t4 → t5: Serial clock counter is reset. Interval value > 30 ns t5 → t6: SPI reset and enabled for read operation. Interval value > 30 ns t7: Internal data transferred to SDA t8: SDA data is stable and can be read After the shifting phase, it is possible to read data, applying 32 serial clocks per data record. Up to 8 data records can be read this way. Eight 32-bit data registers in STPM01 store relevant measurement information (see related datasheet for more details). Figure 5 shows the records structure and the information they hold, the default sequence of reading. The system that reads the data record from the STPM01 should check the integrity of each data record. If the check fails, the reading should be repeated, but this time only the shifting phase should be applied otherwise a new data would be latched into transmission latches and previous reading would be incorrectly lost. Figure 4. Timing for reading data registers t 2 t 1 t 4 t 3 t 6 t 5 t 8 t 7 last bit of 32nd byte 1st byte 1st byte SDA SCL SYN SCS |
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