AN3995 datasheet(13/49 Pages) STMICROELECTRONICS

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AN3995

e200z4d initialization and example code

Doc ID 022384 Rev 2

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Configure the MMU TLB entry for RAM. In this manner, the user code can initialize the

SRAM ECC (see Section 3.1.3: Initialize the SRAM ECC).

Configure the MMU TLB entry for Flash(h) (see Section 3.1.4: Configure MMU for

Flash)

–

Copy configuration code to SRAM(i)

–

Jump to first instruction of this code in SRAM and execute it

–

Transfer execution back to the Flash

Configure the MMU TLB entry for the IPBridge (peripherals space) (see Section 3.1.5:

Configure MMU for Peripheral Bridge)

3.1.2

Configure MMU for SRAM

In order to configure MMU TLB entries, there are four MMU Assist registers (MAS) which

are written with the TLB entry number, start address and size of the MMU entry and other

information such as whether the page is VLE or BookE instructions.

In Figure 3 is showed a scratch code of MMU configuration(j) for RAM using TLB entry 1:

Figure 3.

MMU configuration code for SRAM

The SRAM space mapped through the TLB 1 is half of the space available on the device(k)

and it corresponds to the bank placed at the lower addresses.

The example shown here is using this as the upper bank is reserved for the e200z0h core.

In this application note the strategy suggested is to re-uses the TLB 0 to map all Flash memory space.

User can use this mechanism at this time (the execution from SRAM) to configure the wait states for Flash (see

Section 3.1.7: Performance Hints Initialization): to avoid executing code from Flash while wait states are

changing. This means that should copy also this configuration code to SRAM at this time and execute it with

the MMU ones.

After the MAS registers are written, the TLB is validated with a single “tlbwe” (TLB Write Entry) instruction

This device family has two 128KB contiguous banks start at 0x4000_0000

#/*************************************************************************/

#/* MMU configuration code for SRAM

#/* TLB1, Entry 1 128KB 0x4000_0000 to 0x4001_FFFF

#/*************************************************************************/

e_lis r3, 0x1001

mtmas0 r3

#/* MAS0 */

e_lis r3, 0xC000

e_or2i r3, 0x0380

mtmas1 r3

#/* MAS1 = 0xC0000380 (128Kb) */

e_lis r3, 0x4000

e_or2i r3, 0x0028

mtmas2 r3

#/* MAS2 = 0x40000028 */

e_lis r3, 0x4000

e_or2i r3, 0x003F

mtmas3 r3

#/* MAS3 = 0x4000003F */

tlbwe

#/* Write the entry to the TLB */

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