to minimise leakage inductance.

Also core and coil former geometry play an important role. To achieve good coupling, windings must

be long and thin, and set out in concentric fashion. Therefore geometries with short and thick win-

dows (such as RM, PQ or pot cores) should be avoided while ETD, EFD, EC and the majority of E

cores are good. Furthermore, it is not recommended to use split coil formers, where windings are ar-

ranged side by side.

b) make the primary intrawinding capacitance as low as possible. This is the major component of the

losses, it causes ringing and noise problems that may force the use of additional damping networks

to comply with EMC requirements.

To achieve a low capacitance, always wind first the primary winding and, in particular, the half whose

end is to be connected to the drain of the MOSFET. In this way the second half primary has a shield-

ing effect that reduces the capacitive coupling. In case of multiple layer windings, which exhibit higher

capacitance, it is useful to embed one layer of isolation in between. This, however, tends to increase

leakage inductance and therefore should be done with care. Split coil formers are effective to this end

but, as mentioned earlier, degrade leakage inductance and then should be avoided.

drain of the MOSFET during its OFF-time and the losses on the resistor of the clamp network (if an

RCD type is used, see "Clamp network"). Besides, a lower reflected voltage often leads to a primary-

to-secondary turns ratio closer to 1:1. A positive side effect of that is a better magnetic coupling be-

tween windings, which, in turn, helps reduce leakage inductance. On the other hand, consider that a

lower reflected voltage involves higher primary peak currents at heavy load.

Clamp network.

Typically, the voltage spike due to transformer’s leakage inductance is limited by an RCD clamp (see fig.

12a). Its action should be very light so as to have a spike as large as possible, consistently with the need

of never exceeding the voltage rating of the MOSFET. This will optimize energy transfer from primary to

secondary. A low leakage inductance of the transformer is, of course, extremely helpful.

RCD clamps dissipate power even under no-load conditions: there is always the reflected voltage across

the clamp resistor (R). To reduce clamp losses to a negligible level at light load, the use of a zener

clamp (see fig. 12b) is recommended whenever possible. Such a circuit gives also a well defined clamp-

ing level but, on the other hand, dissipates more power at full load. Its use is therefore limited to low

power applications.

An alternative to these solutions can be the use of a non-dissipative clamp like the LCD one shown in

fig. 12c, which helps also reduce turn-off losses in the MOSFET. This circuit recovers the majority of the

leakage inductance energy by transferring it back onto the input voltage rail through C and D2. There is

just a little power dissipation on the two diodes and the inductor. However, there is a slight increase of

the conduction losses in the MOSFET at heavy load and, besides, the circuit is quite expensive and not

easy to optimise.

R

C

D

RCD CLAMP

D

ZENER

CLAMP

D1

LCD CLAMP

D2

L

C

a)

b)

b)

Figure 12. Possible clamp circuit topologies.

AN1049 APPLICATION NOTE

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