AN1299

To manage below-ground voltage on the OUT pin

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The goal is to reduce the trace parasitic inductance as much as possible, but also to take

into account the amount of the total freewheeling diode recovered charge and the diode

softness factor.

4.2.3

Tricks and layout suggestions

Layout suggestions:

The driver can easily deal with an undershoot spike in the order of -18 V (measured

between the IC OUT pin and its signal ground) for a duration that must not be longer than

100 ns. The guidelines to follow in order to avoid large undershoot spike are:

●

Remember that the total amount of inductance and resistance exhibited is directly

proportional to the trace's length and inversely proportional to its width.

●

Put both power switches of each half-bridge as close as possible in order to make

traces as short and wide as possible between the low-side drain and the high-side

source (this solution is aimed to minimize the stray inductance ParD1 and ParS2 shown

in Figure 22).

●

Pay attention to the traces between the low-side source, the sense resistor, and the

power ground reference, making them shorter and wider (to reduce ParS1, Figure 22).

Remember that all load current flows in this path.

Figure 22.

Path to be optimized

●

Use "inductance free" sense resistors

●

Shorten the power switch lead length

Tricks

●

If we are not able to reduce the below-ground spikes acting only on the layout, a

resistor in series to the OUT pin (as indicated in Figure 23) is a good trick that improves

the device immunity. The resistor is not additional, the part count does not change, but

it is the high side turn-off resistor that is moved on the OUT pin. In this way we can deal

with undershoot spikes exceeding -18 V.

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