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AN1645 - APPLICATION NOTE

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Figure 3: Block Schematic

4. SUPPLY VOLTAGE AND UNDER VOLTAGE LOCK-OUT

The supply input range is from 4V to 5.5V. An internal zener diode limits the maximum voltage to 5.7V.

A 100nF ceramic capacitor must be connected to Vcc and SGLGND pin in order to assure a stable

supply voltage. This capacitor must be placed very close to the device. Another 100nF capacitor is

necessary between Vcc and PWRGND.

Under Voltage Lock Out feature guarantees proper start-up while it avoids undesirable driving during

eventual dropping of the supply voltage.

As shown in the Block Diagram, the Vcc voltage also supplies the two output drivers, consequently the

maximum driving voltage is 5.5V, so the use of logic gate threshold mosfets is recommended.

5. SYNCHRONIZATION

An innovative feature of the STSR2P is the capability to operate in the secondary side without any

synchronization signal coming from the primary side. The IC synchronization is obtained directly from the

secondary side using the voltage across the free wheeling mosfet as the information for the switching

transitions. The Ck pin is the input for the synchronization signal; the internal threshold is set at 2.8V. As

can be seen in figure 3, a Peak Detector is present at the Ck pin. This block is able to distinguish

between the primary mosfet switching transitions and the eventual sinusoidal waveform caused by

discontinuous mode operation (see figure 4). A wrong synchronization causes wrong driving of the

synchronous rectifiers.