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UPD17P401 Datasheet(PDF) 21 Page - NEC |
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UPD17P401 Datasheet(HTML) 21 Page - NEC |
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21 / 32 page ![]() µPD17P401 21 3.3 PROGRAM MEMORY READ PROCEDURE (1) Unused pins are connected to GND with a pull-down resistor. The CLK pin is driven low. (2) 5 V is supplied to the VDD pin. The VPP pin is driven low. (3) 5 V is supplied to the VPP pin after a 10 µs wait. (4) The mode setting pin is set to the program memory address zero-clear mode. (5) 6 V is supplied to VDD, 12.5 V to VPP. (6) Program inhibit mode. (7) Verify mode. When clock pulses are input to the CLK pin, data is output sequentially, one address per 4-input cycle. (8) Program inhibit mode. (9) Program memory address zero-clear mode. (10) VDD/VPP pin voltage is changed to 5 V. (11) Power OFF. Steps (2) to (9) of this procedure are shown in the following Figure. V PP V PP VDD GND + 1 VDD VDD GND VDD CLK D0-D7 MD0 MD1 MD2 MD3 Data Output Data Output “L” |
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