AN3223

Reading and writing to the STCF04 registers through the I²C bus

Doc ID 17553 Rev 2

23/29

9.3

Reading from a single register

The reading operation starts with a START bit followed by the 7-bit device address of the

address + R/W bit by an acknowledge pulse. The address of the register which should be

read is sent and confirmed by an acknowledge pulse from the STCF04 again. Then the

master generates a START bit again and sends the device address followed by the R/W bit,

which is now 1. The STCF04 confirms receipt of the address + R/W bit by an acknowledge

pulse, and starts to send data to the master. No acknowledge pulse from the master is

required after receiving the data. Then, the master generates a STOP bit to terminate the

communication. See

Figure 15 below.

9.4

Reading from multiple registers with incremental addressing

Reading from multiple registers starts in the same way as reading from a single register. As

soon as the first register is read, the register address is automatically incremented. If the

master generates an acknowledge pulse after receiving the data from the first register, then

Figure 14.

Writing to multiple register

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

A

C

K

ADDRESS OF

REGISTER i

DATA i

A

C

K

A

C

K

S

T

O

P

M

S

B

M

S

B

L

S

B

L

S

B

DATA i+1

A

C

K

L

S

B

DATA i+2

A

C

K

L

S

B

DATA i+2

L

S

B

DATA i+n

A

C

K

M

S

B

M

S

B

M

S

B

M

S

B

M

S

B

A

C

K

L

S

B

SDA LINE

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

A

C

K

ADDRESS OF

REGISTER i

DATA i

A

C

K

A

C

K

S

T

O

P

M

S

B

M

S

B

L

S

B

L

S

B

DATA i+1

A

C

K

L

S

B

DATA i+2

A

C

K

L

S

B

DATA i+2

L

S

B

DATA i+n

A

C

K

M

S

B

M

S

B

M

S

B

M

S

B

M

S

B

A

C

K

L

S

B

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

A

C

K

ADDRESS OF

REGISTER i

DATA i

A

C

K

A

C

K

S

T

O

P

M

S

B

M

S

B

L

S

B

L

S

B

DATA i+1

A

C

K

L

S

B

DATA i+2

A

C

K

L

S

B

DATA i+2

L

S

B

DATA i+n

A

C

K

M

S

B

M

S

B

M

S

B

M

S

B

M

S

B

A

C

K

L

S

B

SDA LINE

AM07808v1

Figure 15.

Reading from a single register

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

ADDRESS

OF

REGISTER

A

C

K

M

S

B

L

S

B

S

T

A

R

T

A

C

K

R

/

W

R

E

A

D

DEVICE

ADDRESS

7 bits

DATA

L

S

B

S

T

O

P

N

O

A

C

K

SDA LINE

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

ADDRESS

OF

REGISTER

A

C

K

M

S

B

L

S

B

S

T

A

R

T

A

C

K

R

/

W

R

E

A

D

DEVICE

ADDRESS

7 bits

DATA

L

S

B

S

T

O

P

N

O

A

C

K

SDA LINE

AM07809v1