AN4009

STEVAL-IFP019V1 demonstration board description

Doc ID 022458 Rev 1

13/23

Figure 13.

Burst timing waveform

Table 3 shows the results of an inherent burst test. Normal performance has been observed

when applying four different disturbance levels on the output ports and Vcc main voltage

power supply.

Note:

1

Outputs floating.

2

To reach same results reported in the tables above, it is necessary to replace C7 and C8

with two high voltage capacitors.

Note:

Outputs loaded by 1 k

Ω resistors.

Table 3.

Application EFT (burst) robustness, applied to supply voltage lines

Configuration

EFT test signal amplitude, test result @ polarity (+/-)

1 kV

2 kV

3 kV

4 kV

5 kV

Standard

A / A

A / A

A / A

B / B

B / B

Primary and secondary GNDs

shorted

A / A

A / A

B / A

B / B

B / B

Table 4.

Application EFT (burst) robustness, applied to output lines

Configuration

EFT test signal amplitude, test result @ polarity (+/-)

1 kV

2 kV

3 kV

4 kV

5 kV

Standard

A / A

A / A

B / B

B / B

B / B