AN4163 datasheet(13/33 Pages) STMICROELECTRONICS

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AN4163

Test results and significant waveforms

To overcome this issue the device forces the PFC pre-regulator to process more energy

near the line voltage zero-crossings as compared to that commanded by the control loop.

This will result in both minimizing the time interval where energy transfer is lacking and fully

discharging the high-frequency filter capacitor after the bridge. Essentially, the circuit

artificially increases the ON-time of the power switch with a positive offset added to the

output of the multiplier in the proximity of the line voltage zero-crossings. This offset is

reduced as the instantaneous line voltage increases, so that it becomes negligible as the

line voltage moves toward the top of the sinusoid and it is modulated by the voltage on the

VFF pin, so as to have little offset at low line, where energy transfer at zero-crossings is

typically quite good, and a larger offset at high line where the energy transfer gets worse.

To derive maximum benefit from the THD optimizer circuit, the high-frequency filter

capacitors after the bridge rectifier should be minimized, compatible with EMI filtering

needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input

current in itself, thus reducing the effectiveness of the optimizer circuit.

2.3

Switching frequency and TIMER pin

With the L4984D the switching frequency is determined by a capacitor connected between

the TIMER pin and ground, charged by an accurate internal generator (ITIMER) of 156 A

(typ.) during the OFF-time, generating a voltage ramp. As shown in Figure 22 when the

voltage ramp on TIMER equals the voltage on the MULT pin, connected through a resistive

divider to the rectified mains to get a sinusoidal voltage reference, the OFF-time of the

power MOSFET is terminated, the gate driver (GD) pin is driven high and the ramp resets at

zero. The timing capacitor CT is then selected with the following formula described in the

L4984D datasheet:

Equation 1

where fSW is the switching frequency and kp the ratio of the resistive divider on the MULT

pin, calculated considering the maximum value of the multiplier input, that is the voltage

measured on the MULT pin at maximum mains voltage. The switching frequency fSW is not

constant but is modulated at twice the line frequency ripple 2fL appearing across the output

capacitor Cout, spreading the spectrum of the electrical noise injected back into the power

line and facilitating the compliance with conducted EMI emission regulations. The switching

frequency chosen for this design is around 70 kHz, so the capacitor on the TIMER pin

needed to obtain the desired frequency is:

Equation 2

An NP0 capacitor with commercial value of 680 pF has been selected for the TIMER

capacitor. For further details on the calculation procedure of the entire converter, please

refer to AN4149, “Designing a CCM PFC pre-regulator based on the L4984D”.

TIMER

Psw

kVout f



156 A

695pF

8 10

400V 70kHz









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