13/17

MIGRATING APPLICATIONS FROM ST72511/311/314/124 TO ST72521/321/324

5.2.2 External Interrupt

A single EICR register manages all the features linked to the external interrupt sources (I/O

port interrupt sensitivity and TLI)

5.2.3 SPI/SS pin

The SPI SS pin alternate function is controlled from the SPI peripheral in the SPICSR register.

6 I/O PORT

6.1 EXTERNAL INTERRUPT HANDLING

To guarantee upward compatibility, the three following points have to be taken into account

when you develop your application software:

– In the ST72511/311R, 314N, 314/124J, parasitic interrupts occur when software changes

the I/O port configuration. In the ST72521/321R, 321/324J, these parasitic interrupts no long-

er occur.

– In the ST72511/311R, 314N, 314/124J, the IPA and IPB control bits can be written at any

time. In the ST72521/321R, 321/324J, these two bits can be written only when interrupts are

masked (I[1:0]=”10” in the CC register).

– In the ST72521/321R, 321/324J pending interrupts are cleared by software changing the val-

ue of the ISx[1:0], IPA or IPB bits. In the ST72511/311R, 314N, 314/124J this is the case

only for the ISx[1:0] bits.

7 PERIPHERALS

7.1 16-BIT TIMER

The 16-bit timer of the ST72511/311R, 314N, 314/124J has been modified in the ST72521/

321R, 321/324J to solve some issues related to PWM and One Pulse modes. If you use either

of these two modes, you may need to change your software when transferring code from the

ST72511/311 to the ST72521/321.

ST72324J family devices have one limitation versus ST72314/124J: in ST72324J, Input Cap-

ture 2 (IC2) and Output Compare 2 (OC2) functions are not available on Timer A.

All other modes of the timer do not change.

7.1.1 PWM Mode

To avoid any uncontrolled status on the PWM output, a double buffering on the output com-

pare registers (2 x 16 bits) is implemented in the ST72521/321R, 321/324J. This double buff-

ering is not present in the ST72511/311R, 314N, 314/124J.