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GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264

Note: The timing variation shown in Figure 3. is due to the unknown status of the prescaler when writing

to the CR register.

WHERE:

CNT = Value of T[5:0] bits in the WDGCR register (6 bits)

MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits

in the MCCSR register

IF

THEN

ELSE

IF

THEN

ELSE

Note: In the above formulae, division results must be rounded down to the next integer value.

Example:

With 2ms timeout selected in MCCSR register

TB1 Bit

(MCCSR Reg.)

TB0 Bit

(MCCSR Reg.)

Selected MCCSR

Timebase

MSB

LSB

0

0

2ms

4

59

0

1

4ms

8

53

1

0

10ms

20

35

1

1

25ms

49

54

Value of T[5:0] Bits in

WDGCR Register (Hex.)

Min. Watchdog

Timeout (ms)

Max. Watchdog

Timeout (ms)

00

1.496

2.048

3F

128

128.552

CNT

MSB

4

-------------

<

t

min

t

min0

16384

CNT

t

osc2

×

×

+

=

t

min

t

min0

16384

CN T

4 CNT

MSB

-----------------

–





×

192

L SB

+

() 64

4CNT

MSB

-----------------

×

×

+

t

osc2

×

+

=

CNT

MSB

4

-------------

≤

t

max

t

max0

16384

CNT

t

osc2

×

×

+

=

t

max

t

max0

16384

C NT

4CNT

MSB

-----------------

–





×

192

LSB

+

() 64

4CNT

MS B

-----------------

×

×

+

t

o sc2

×

+

=