AN1526 datasheet(23/26 Pages) STMICROELECTRONICS

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ST7FLITE0 QUICK REFERENCE NOTE

Figure 16. SPI

SPI DATA I/O REGISTER

SPIDR (@ 0031h, Read/Write)

RESET VALUE = XXh

SPI DATA

SPI CONTROL REGISTER

SPICR (@ 0032h, Read/Write)

RESET VALUE = 0Xh

SPR0

CPHA

SPR1

MSTR

SPR2

SPE

SPIE

CPOL

0 = INTERRUPT DISABLED

1 = INT. GEN. WHEN SPIF = 1 OR MODF = 1

0 = I/O PORT CONNECTED TO PINS

1 = SPI ALT. FUNCTION CONNECTED TO PINS

0 = SLAVE MODE SELECTED

1 = MASTER MODE SELECTED

00 = SERIAL PERIPHERAL RATE = fCPU / 8

01 = SERIAL PERIPHERAL RATE = fCPU / 16

10 = SERIAL PERIPHERAL RATE = fCPU / 64

11 = SERIAL PERIPHERAL RATE = fCPU / 128

0 = DIVIDER BY 2 ENABLED

1 = DIVIDER BY 2 DISABLED

0 = STEADY STATE IS LOW

1 = STEADY STATE IS HIGH

0 = DATA CAPTURE ON 1ST CLOCK TRANSITION

1 = DATA CAPTURE ON 2ND CLOCK TRANSITION

SPI CONTROL/STATUS REGISTER

SPICSR (@ 0033h, Read Only)

RESET VALUE = 00h

SSI

SOD

SSM

MODF

OVR

WCOL

SPIF

0 = DATA TRANSFER IN PROGRESS

1 = DATA TRANSFER COMPLETED

0 = NO WRITE COLLISIONS DETECTED

1 = A WRITE COLLISION HAS BEEN DETECTED

0 = NO MASTER MODE FAULTS DETECTED

1 = A MASTER MODE FAULT HAS BEEN DETECTED

0 = HARDWARE MODE

1 = SOFTWARE MODE

0 = SLAVE SELECTED

1 = SLAVE NOT SELECTED

0 = NO OVERRUN ERRORS

1 = AN OVERRUN ERROR HAS BEEN DETECTED

RESERVED, MUST BE SET TO 0

0 = SPI OUTPUT NOT DISABLED

1 = SPI OUTPUT DISABLED

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