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ST92F120/F124/150/F250 TESTFLASH

The Code Update routine also remaps the interrupts in TestFlash (ISR = 23h), and configures

pins 3 (SOUT0) and 4 (CLKOUT0) of Port 5 as Alternate Function.

The Code Update routine uses 4 Interrupt routines: SCI Receiver Error Interrupt routine

(vector in 0010h), SCI Address Match Interrupt routine (vector in 0012h), SCI Receiver Data

Ready Interrupt routine (vector in 0014h), SCI Transmitter Buffer Empty Interrupt routine

(vector in 0016h).

3.4 E3TM INITIALIZATION ROUTINE (230026H)

Inputs: None.

Outputs: R0.

Variables: R1-R47, R160-R223 (for Stack).

Goal: to initialize the E3TM Hardware Emulation.

This routine is automatically called by the Power-On routine, but it can be also called by any

other routine through a far call:

CALLS

23h, 0026h

;E3

TM Init

The E3TM Initialization routine performs the following operations:

■

read the NVCSS1 registers of sector E0 (229003h) and E1 (22D003h);

■

if the values of the two NVCSS1 registers are not coherent, the routine returns with the Error

Code 40h, without completing the E3TM Initialization;

■

if an aborted erase phase is detected, a Sector Erase operation is performed on the bad

sector;

■

write the VCSS1 register (222003h) with the sector number currently mapping the E3TM

data;

■

read the NVCSS0 registers of sector E0 (229001h) and E1 (22D001h);

CHCR - R250

83h

8 Data Bits

CCR - R251

E8h

rec. clock: ext RXCLK0

trx clock: int CLKOUT0

BRGHR - R252

00h

BRGLR - R253

04h

Baud Rate Divider is 4

SICR - R254

83h

Synchronous Mode

SOCR - R255

01h

Table 3. SCI0 Registers (page 24) initialization

Value

Notes

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