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INTERRUPT HANDLING FOR STR7 MICROCONTROLLERS

*(IRQChannel+0x3C)=1<< (* IRQChannel ); // clear the interrupt

}

The next example shows the compiler output without the __irq keyword:

STR

r14,[r13,#-4]!

LDR

r2,0xe4c

LDR

r0,[r2,#0]

CMP

r0,#0

BLEQ

Channel0_IRQHandler

LDR

r0,[r2,#0]

MOV

r1,#1

MOV

r0,r1,LSL r0

STR

r0,[r2,#0xf0]

LDR

pc,[r13],#4

The compiler output with the __irq keyword:

STRMFD

sp!,{r0-r4,r12,lr}

LDR

r2,0xe4c

LDR

r0,[r2,#0]

CMP

r0,#0

BLEQ

Channel0_IRQHandler

LDR

r0,[r2,#0]

MOV

r1,#1

MOV

r0,r1,LSL r0

STR

r0,[r2,#0xf0]

LDMFD

sp!,{r0-r4,r12,lr}

SUBS

pc,lr,#4

In the first example only the link register is saved to the stack then restored to the PC on re-

turn, however with the use of the __irq label, seven registers, including the link register, are

saved to the stack. Finally and after restoring them, a data processing instruction, with the S

bit set, is used to return from the exception handler.

6 INTERRUPT HANDLING USING THE EIC

6.1 EIC OVERVIEW

This section of the application note covers the IRQ handling using the EIC. The Enhanced In-

terrupt Controller has hardware handling of multiple interrupt channels, interrupt priority and

automatic vectorization.

When a peripheral generates an interrupt, an IRQ line is set. If the corresponding bit is set in

the Interrupt Enable Register (IER) then the related bit in the IPR register will be set to 1. A pri-

ority check by the EIC then follows to test if this interrupt priority is to be accepted. If the inter-

rupt is accepted, the IRQ line is asserted low to the ARM core, and the IVR[15:0] register is up-

dated with the contents of the SIRn[31:16] register for the related interrupt channel, resulting

in a new Interrupt Vector.