2 ST72F321 Migration: feature overview

AN2187

4/13

2

ST72F321 Migration: feature overview

Table 3.

ST72F321 Migration: feature overview

“-” stands for: No change vs. ST72F321, fully compatible with existing development

Note 1: Refer to the corresponding datasheets for more information.

Note 2: Exit from Active Halt available with external interrupts (see Section 7)

Note 3: improved ADC accuracy

ST72F321

ST72F321B

ST72F325

Package

TQFP44 / TQFP64

-

-

Program Memory

32K to 60KFlash

-

16K to 60K Flash

Operating Supply

3.8 V to 5.5V

-

-

Register Map

128 bytes

-

-

I/Os (High sink)

48/32 pins

-

-

Power saving Modes

Slow / Wait / Active Halt /

Halt

Nested Interrupts

Yes

-

-

MCC / RTC

Yes

-

-

Watchdog

Yes

-

-

16-bit Timer

(OC / IC / PWM)

2 Timers (3 / 3 / 2)

-

-

8-bit PWMART

(OC / IC / PWM)

1 Timer (4 / 0 / 4)

-

-

SPI

Yes

-

-

SCI

Yes

-

-

Yes

-

-

ADC

Yes (10-bit)

LVD

3 Levels

-

-

CSS

No

-

Yes

Development tools

ST7MDT20x-EMU3 and ST7MTD20-DVP3

ST7232X-SK/RAIS

ST7MDT20x-EPB and ST7MTD20-DVP3