AN2202

2 Clock management

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2

Clock management

The following figure provides an overview of the clock management block of the STR73x:

Figure 3.

Clock management block

Legend:

2.1

Clock configuration & power management

Different clock configurations are provided by the STR73x MCU offering the means to optimize

the power consumption in the device, the main features are:

●

Individual peripheral clock disabling.

●

Up to three low power system clocks: CLK2, CLK2/16 and the PLL Free running mode

clock (refer to the PRCCU section in the STR73x reference manual for details on the PLL

free running mode).

2.2

Disabling peripherals clocks

The peripheral clock managing registers (PCGR0 and PCGR1 of the configuration registers)

allows each module clock of the device to be switched on/off individually. Refer to the

Configuration Registers section in the STR73x reference manual.

Note: 1 PLL is automatically disabled when:

- The Main Voltage Regulator (MVR) is stopped

- Entering LPWFI, STOP or HALT low power modes

- When PRCCU_PLLCR DX[2:0] bits are set to ‘111’ and FREEN bit is reset

2 When not using the RC clock, you can disable it by setting bit RCHSE and/or RCSS in the

PCU_CTRL register.

1/2

PLL

XTAL1

XTAL2

1/16

PRESCALER

PRCCU

Main

Oscillator

RC

Oscillator

Back Up

CMU

WAKE Up Timer