AN2442

DMA unit

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7.

A DMA terminal count interrupt or a DMA error interrupt can be generated:

DMA_ITConfig(DMA_Channelx, ENABLE);

The following part of the code example shows how to configure the UART-TX DMA interface

on channel0 with interrupt generation when DMA count reach 0.

/******************* Example DMA Config ***********************/

/* No next linked list item*/

DMA_struct.DMA_Channel_LLstItm= 0;

/* Source address of the DMA transfer */

DMA_struct.DMA_Channel_SrcAdd=(u32)(&TxBuffer0[0]);

/* Destination address of DMA the transfer is UART Data reg*/

DMA_struct.DMA_Channel_DesAdd=(u32)(&UART0->DR);

/* Source data width is Byte */

DMA_struct.DMA_Channel_SrcWidth= DMA_SrcWidth_Byte;

/* Destination bus width is Byte */

DMA_struct.DMA_Channel_DesWidth= DMA_DesWidth_Byte;

/* DMAC is The flow controller*/

DMA_struct.DMA_Channel_FlowCntrl=DMA_FlowCntrl1_DMA;

/*The DMAC is triggered by the SSP_DMA_Transmit request.*/

DMA_struct.DMA_Channel_Des= DMA_DES_UART0_TX;

/*Transfer size of 12 data */

DMA_struct.DMA_Channel_TrsfSize =12;

/* Update the DMA channel0 registers with DMA_struct values */

DMA_Init(DMA_Channel0,&DMA_struct);

/* Enable Source increment */

DMA_ChannelSRCIncConfig (DMA_Channel0, ENABLE);

/*Enable the Terminal Count interrupt*/

DMA_ITConfig(DMA_Channel0, ENABLE);

DMA_ITMaskConfig(DMA_Channel0, DMA_ITMask_ITC, ENABLE);

/*Enable the DMA channel0*/

DMA_ChannelCmd (DMA_Channel0,ENABLE);