AN2593

Software recommendations for handling interrupts

9/15

The IENABLE macro ensures the reenabling of interrupts in system mode in order to allow

interrupt nesting. IDISABLE disables IRQs when exiting from the interrupt service routine

and returning to IRQ mode.

#define IENABLE asm(" MRS LR, SPSR"); /* Copy SPSR_irq to LR */ \

asm("STMFD SP!, {LR} "); /* Save SPSR_irq */ \

asm("MSR CPSR_c, #0x1F ");

/* Switch to SYS mode with IRQ enabled*/ \

asm("STMFD SP!, {LR} ") ;

/* Save SYS mode LR */

#define IDISABLE asm("LDMFD SP!, {LR}") ;

/* Restore SYS mode LR */ \

asm("MSR CPSR_c, #0x92") ; /* Switch to IRQ mode with IRQ disabled*/ \

asm("LDMFD SP!, {R0}") ;

/* Restore SPSR_irq to R0 */ \

asm("MSR SPSR_cxsf, R0") ; /* Copy R0 to SPSR_irq */

Example

: Timer0 interrupt (interrupt on VIC0)

void TIM0_IRQHandler (void)

{

/* switch to system mode with IRQ enabled*/

IENABLE;

/* clear interrupt flag and process interrupt */

...

...

...

/* switch to IRQ mode with IRQ disabled*/

IDISABLE;

/* write any value to VIC0 Vector address register */

VIC0->VAR = 0xFF

}

2.3.2

Without interrupt nesting support

If your application does not need nested interrupt support then you should not insert the

IENABLE and IDISABLE macros.

But you still need to write any value to VIC0 Vector Address register at end of interrupt

processing, if the interrupt originates from VIC0, this is in order to update the VIC0 priority

logic after reading the VIC0 Vector Address in order to jump to the interrupt service routine.

Because there is no priority managment to be done, you are not obliged to do a read of

VIC1 Vector address register at the start of a VIC1 interrupt service routine nor to do a write

to this register at the end of interrupt processing.