AN2595 - Application note

Port0 startup configuration

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2

Port0 startup configuration

A reset sequence may be triggered for the following reasons:

●

Hardware reset signal on pin RSTIN (hardware reset input)

●

Execution of the software reset instruction SRST

●

Overflow of the Watchdog Timer

After recognition of a reset, the ST10F27xZx proceeds with the actions listed below:

●

Complete internal RAM write operation before the internal reset procedure begins

●

Cancel pending internal hold states

●

Abort external memory access cycles

●

Start program execution from memory location 0000h in code segment 0

Note:

Please refer to the datasheet and user’s manual for reset event definitions.

2.1

Port0

Pull-down resistors

Pull-down resistors should be low enough so that the input voltage in P0.x is within the

circuit specification when taking into account the circuit pull-up current (see PORT0

connected to PORT0 pins.

the calculated result, are 10 K

Ω.

Pull-up resistors

PORT0 supplies internal pull-up resistors that are active during Reset. Pull-up resistors

should be low enough so that the input voltage in P0.x is within the circuit specification when

worst case evaluation, leakage current from other external circuits should always be added

to circuit leakage current.

Table 2 presents the clock options on PORT0 P0H5 - P0H7 for devices with low power

oscillator.

Table 3 presents the clock options on PORT0 P0H5 - P0H7 for devices with wide-swing

oscillator.