AN2674

DDR memory interface

Doc ID 14204 Rev 2

7/22

Traces routed near the edge of a reference plane should maintain at least 30 mil gap to the

edge of the reference plane.

To minimize the reflection all the traces should have an impedance of 55 Ohm ± 10%.

Data lanes:

DL0: Data Lane 0 includes DQ0-DQ7, LDQS-LDQSn, LDM.

Route these signals on the same layer(s), with similarly located layer transitions if they

exist.

Length/timing skew: This set of signals traces must have their lengths matched to

within 2.5 mm or 100 mils (approximately 15 ps).

DL1: Data Lane 1 includes DQ8-DQ15, UDQS-UDQSn, UDM.

Route these signals on the same layer(s), with similarly located layer transitions if they

exist.

Length/timing skew: This set of signals traces must have their lengths matched to

within 1.5 mm or 60 mils (approximately 10 ps).

Note:

Trace lengths for different clock domains are not required to be matched. Trace lengths for

DB0 do not need to match the trace lengths for DB1. Trace lengths for address/command

signals do not need to match trace lengths for DB0 or DB1. Use minimum trace lengths

within each clock domain.

CLK/CLK# and DQS/DQS#

CLK/CLK# and DQS/DQS# signals should be routed as differential pairs, length matched.

GATE_OPEN(0,1)

GATE_OPEN(0,1) must be left unconnected. Do not connect any trace, via, or test point to

balls Y13 and Y17.

2.3

Trace length matching

The SPEAr3xx package substrate does not have equal-length DDR signal traces. To insure

timing alignment for all signals, both the substrate trace length plus the PCB trace length for

each signal must be equalized to meet the trace length skew tolerance for all signals within

the clock domain. A procedure for accomplishing this is provided below, along with a

worksheet to facilitate this process during DRAM interface layout. The procedure may

require an iteration if the initial longest trace must be lengthened to accommodate

serpentine routing of other signals.

To determine trace length matching requirements for each signal, follow these steps,

utilizing the worksheet provided. Ltol (maximum length difference within a clock domain) is

2.5 mm, or 100 mils.

1.

Route signals per above guidelines, using the shortest possible length on all signals at

this step (length equalizing is done later).

2.

Tabulate the lengths of all traces that were routed in step 1, by filling in worksheet in the

column labeled "INITIAL SHORTEST PCB TRACE LENGTH", and "PCB VIA

LENGTHS".