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M66591GP Datasheet(PDF) 21 Page - Renesas Technology Corp |
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M66591GP Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 135 page ![]() M66591GP Rev .1.00 Nov . 30, 2004 page 19 of 131 2.7 Data Pin & FIFO/DMA Control Pin Configuration Register 0 Data Pin & FIFO/DMA Control Pin Configuration Register 0 (PinCtrlCfg0) <Address: H’08> b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0 PA [7:0] 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - <H/W reset: H’00??> <S/W reset: -> <USB bus reset: -> b Bit name Function R W 15~8 Reserved. Set it to “0”. “0” “0” 7~0 PA [7:0] General port A 0: Low level 1: High level The port number corresponds to the bit number. b0: PA0 pin b1: PA1 pin b2: PA2 pin b3: PA3 pin b4: PA4 pin b5: PA5 pin b6: PA6 pin b7: PA7 pin (1) PA [7:0] (General Port A) Bits (b7-b0) When the DB_Cfg bit of the Data Pin & FIFO/DMA Control Pin Configuration Register 1 is set to “0” (GPIO), the SD7-SD0 pins are assigned to general purpose port PA [7:0]. Since general purpose port has a separate buffer for input and output, when the port is set to input, the read data is always the state of input pins even if any data is written to these bits. The output buffer of general purpose port is undefined after H/W reset. It is necessary to write initial value before change direction to output, when using as output port. And, the value is undefined when reading from output port. |
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