AN3002

Doc ID 15912 Rev 2

7/22

2

This feature is controlled by the I2C_Write_Lock bits stored in the 8 bytes of the

I2C_Write_Lock bit area starting from the location 2048 (see Table 2). Using these 64 bits, it

is possible to write-protect all the 64 sectors in the M24LRxx memory.

the corresponding sector is unprotected. When the bit is set to 1, the corresponding sector

is write-protected.

must have the E2 Chip Enable address at 1.

On delivery, the default value of the 8 bytes of the I2C_Write_Lock bit area is reset to 00h.

2.1

M24LRxx I2C password security

2.1.1

M24LRxx in order to modify the write access rights of all the memory sectors protected by

the I2C_Write_Lock bits, including the password itself. If the presented password is correct,

Present Password command is issued.

Following a Start condition, the bus master sends a device select code with the Read/Write

bit (RW) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown

responds to each address byte with an acknowledge bit, and then waits for the 4 password

data bytes, the validation code, 09h, and a resend of the 4 password data bytes. The most

significant byte of the password is sent first, followed by the least significant bytes.

It is necessary to send the 32-bit password twice to prevent any data corruption during the

sequence. If the two 32-bit passwords sent are not exactly the same, the M24LRxx does not

start the internal comparison.

Table 2.

I2C_Write_Lock bit

Bits [31:24]

Bits [23:16]

Bits [15:8]

Bits [7:0]

E2 = 1

2048

sectors 31-24

sectors 23-16

sectors 15-8

sectors 7-0

E2 = 1

2052

sectors 63-56

sectors 55-48

sectors 47-40

sectors 39-32