AN3100

DDR overview

Doc ID 16606 Rev 2

7/24

transfer data rate or bandwidth. As in the case of DDR SDRAM vs. SDRAM, the bandwidth

of DDR2 memory can double the bandwidth of DDR. DDR already operates on both the

rising and the falling edge of the clock, so DDR2 can achieve twice the bandwidth by

doubling the I/O buffer frequency. DDR2 utilizes a “4-bit prefetch” architecture: this means

that 4 bits of data are moved from the memory array to the I/O buffer per data line for each

core clock cycle. The core clock cycle refers to the cycle time of the memory array, and the

frequency of the memory array is half of the I/O buffers and ¼ of the data rates.

The table below compares the main features of DDR1 and DDR2. Section 2.1.1 and

Section 2.1.2 give more details on the package and power supply differences.

Table 3.

DDR1 and DDR2 at a glance

Features

DDR1

DDR2

Frequency specifications

Data rate

200/266/333/400 Mbps

400/533/667 Mbps

Bus frequency

100/133/166/200 MHz

200/266/333 MHz

DRAM core frequency

100/133/166/200 MHz

100/133/166 MHz

Prefetch size

2 bit

4 bit

Burst length

2/4/8

4/8

Data strobe

Single DQS

Differential Strobe: DQS, /DQS

CAS latency

1.5, 2, 2.5

3, 4, 5

Write latency

1T

Read latency-1

Power Specs

Core voltage (VDD)

2.5 V

1.8 V

I/O voltage (VDDQ)

SSSTL_2(2.5 V)

SSSTL_1.8(1.8 V)

Format

Packaging

TSOP(II), TBGA

FBGA

Compatibility with DDR1

Command Set

Same as DDR1

Parameters

Same as DDR1

Bus Utilization and Signal Integrity

New features

ODT

OCD calibration

Posted CAS

Additive latency