AN3117

DMA controller description

Doc ID 16846 Rev 4

9/28

Figure 1.

Bus system and peripherals supporting DMA

1.

Peripherals available on medium+ and high density devices only. AES available on STM8L162xx only.

2.

Not available on STM8L05xxx devices.

The DMA is able to transfer data from the memory to a peripheral.

●

For regular DMA channels (0, 1 and 2), data transfer can be from (or to) a part of the

RAM memory (see note1).

●

For memory DMA channel (channel 3), 2 cases are available:

a)

When a peripheral-to-memory or memory-to-peripheral transfer is performed, the

memory areas can be all addressable areas (see note 2).

b)

When a memory-to-memory transfer is performed, the source memory areas are

all addressable areas (see note 2), while the destination memory areas are the

first 8 Kbytes (see note 3).

Note:

1

For medium and medium+ density devices, 2-Kbyte RAM memory is accessible (between

0x0000 and 0x07FF).



For high density devices, 4-Kbyte RAM memory is accessible (between 0x0000 and

0x0FFF).

2

Source memory addressable areas are comprised between 0x0000 and 0xFFFF for

medium density devices and between 0x0000 and 0x17FFF for high density devices.

3

Destination memory addressable areas are comprised between 0x0000 and 0x1FFF, which

corresponds to the RAM and the Data EEPROM.

MS30984V1

STM8 core

RAM memory

Program and

Flash memory

DMA1

Ch.1

DMA1 rq1

DMA1 rq2

DMA1 rq3

DMA1 rq4

Peripheral bus

RAM bus

Program bus

DMA1 bus

Peripherals supporting DMA

ADC1

DAC

SPI1

I2C1 USART1

TIM1

TIM2

TIM3

TIM4

Ch.2

Ch.3

Ch.4

Arbiter

TIM5

1)

SPI2

1)

USART2

USART3

AES

1)

1)

1)

2)