AN3140

Status register interrupt bit clear issue

Doc ID 16997 Rev 1

11/14

TIMER_STATUS_INT_ACK register. This '1' is synchronously captured by

TIMER_STATUS_INT_ACK and the interrupt request is generated.

The status '1' is permanently kept inside the register by the feedback structure, until the

interrupt clear operation is performed. The clear operation consists in a write '1' on the

TIM1_ACK_reg through PD_IN input. The output of TIM1_ACK_reg goes to the

TIMER_STATUS_INT_ACK register and clears it.

The feedback structure between TIM1_ACK_reg and ACK_RES_reg ensures that the

output '1' on TIM1_ACK_reg is kept till it is not properly captured by ACK_RES_reg. If

ACK_RES_reg and TIMER_STATUS_INT_ACK reg are balanced in terms of clock skew

(less than 2 ps in wc), the proper capturing of ACK_RES_reg will guarantee the proper

capturing of TIMER_STATUS_INT_ACK.

This structure is supposed to limit the effect of the lack of synchronization between the two

clocks, but it still has one limit: the metastability.

When the data arrives to the FF input pins of both ACK_RES_reg and

TIMER_STATUS_INT_ACK reg simultaneously with TIMER_clk, the behavior of the FF is

not predictable. The only thing we can guarantee is that after 1-2 ns the FF goes to a stable

value but this value is unpredictable.

The static timing analysis on the two registers showed that the datapath 1 on the

ACK_RES_reg is slightly faster than the datapath 2 on the TIMER_STATUS_INT_ACK

register. This means that the ACK_REG_reg has higher chances to properly capture the

correct values in the metastability windows.

Only in this specific situation, for example when ACK_RES_reg captures '1' while

TIMER_STATUS_INT_ACK misses the capture, the issue is present because

ACK_RES_reg drives TIM1_ACK_reg to '0', definitively preventing

TIMER_STATUS_INT_ACK from getting cleared.

Assuming that the critical event is when the TIMER_clk phase is equal to the APB_clk

phase + datapath 2, it is possible to estimate the occurrence of this event.

Within a period of 16 TIMER_clk cycles (or equivalently 25 APB_clk cycles) the two clocks

get realigned. Within this "periodical window" the phase differences of the two clock edges

change from 0 to 13.3 ns (75 MHz period) with a granularity of about 833 ps. Considering

the metastability window of less than 300 ps (FF setup+hold requirement), we can state that

the critical event can happen only once within this window, if for example the occurrence is

1/16.

6.2

Proposed solution

The proposed solution is simple. Two successive write '1' operations guarantee that one of

the two writes is successful. The atomic sequence of the two operations is mandatory, no

further operation can occur between. Knowing that each write operation takes 3 APB_clk

cycles, this double write operation ensures that both writes occur in a single "periodical

window" (16 TIMER_clk or 25 APB_clk).

About current Puppy Linux solution (8 successive write '1' operations), this is not critical at

all: once a write '1' succeeds, the next write '1' operations are not sensed at

TIMER_STATUS_INT_ACK thanks to its feedback structure, so no risk of metastability can

further happen.