AN3261 datasheet(4/17 Pages) STMICROELECTRONICS

4 / 17 page

Features

AN3261

4/17

Doc ID 17837 Rev 1

Features

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The Smart Reset™ functionality is a feature that introduces a reset output response

delay. Both of the Smart Reset™ input buttons must be pressed for a defined tSRC

period, only after which an output reset pulse is generated. This results in a robust

hardware reset. The reset function can then be assigned to the existing keys of a

device, which eliminates the traditional reset hole in the back cover of the device, while

maintaining system stability. All the STM65xx family devices have this feature with the

exception of the STM6504.

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The edge trigger functionality is a reset input with an immediate reset response and a

special debounce feature. Found only on the STM6504 (a device with single-button

edge trigger immediate reset and a single-button delayed Smart Reset™ input,

independent but with a common reset output).

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VCC monitoring/undervoltage reset. When the monitored VCC voltage drops below

the factory-programmed undervoltage reset threshold VRST, the reset output(s)

immediately go active and remain so until VCC rises above VRST and hysteresis, plus

the defined tREC period.

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Battery-low detection is an additional independent voltage monitoring function with a

dedicated battery-low detection output pin. It works as a pure comparator with

VREF=1.25 V. STM6505 only.

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Fixed input logic levels are suitable for configurations where the device driving the

input buttons (keyboard) is connected to a lower voltage than the supply voltage of the

STM65xx device. This is in contrast to the devices with the standard CMOS input logic

levels that are relative to VCC and are suitable only for applications in which the device

driving the inputs of the Smart Reset™ device is powered by the same voltage supply.

AN3261 Datasheet(PDF) 4 Page - STMicroelectronics