PM0056 datasheet(10/156 Pages) STMICROELECTRONICS

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PM0056

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DocID15491 Rev 5

Figure 1. STM32 Cortex-M3 implementation

To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements

tightly-coupled system components that reduce processor area while significantly improving

interrupt handling and system debug capabilities. The Cortex-M3 processor implements a

version of the Thumb® instruction set, ensuring high code density and reduced program

memory requirements. The Cortex-M3 instruction set provides the exceptional performance

expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit

microcontrollers.

The Cortex-M3 processor closely integrates a configurable nested interrupt controller

(NVIC), to deliver industry-leading interrupt performance. The NVIC includes a

non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels. The tight

integration of the processor core and NVIC provides fast execution of interrupt service

routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the

hardware stacking of registers, and the ability to suspend load-multiple and store-multiple

operations. Interrupt handlers do not require any assembler stubs, removing any code

overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead

when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a

deep sleep function that enables the STM32 to enter STOP or STDBY mode.

1.3.1

System level interface

The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide

high speed, low latency memory accesses. It supports unaligned data accesses and

implements atomic bit manipulation that enables faster peripheral controls, system

spinlocks and thread-safe Boolean data handling.

1.3.2

Integrated configurable debug

The Cortex-M3 processor implements a complete hardware debug solution. This provides

high system visibility of the processor and memory through either a traditional JTAG port or

a 2-pin Serial Wire Debug (SWD) port that is ideal for small package devices.

Processor

core

Embedded

Trace Macrocell

NVIC

Debug

access

port

Serial

wire

viewer

Bus matrix

Code

interface

SRAM and

peripheral interface

Data

watchpoints

Flash

patch

STM32 Cortex-M3

processor

ai15994

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