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PM0056 Datasheet(PDF) 147 Page - STMicroelectronics |
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PM0056 Datasheet(HTML) 147 Page - STMicroelectronics |
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147 / 156 page  DocID15491 Rev 5 147/156 PM0056 Core peripherals 4.4.12 Memory management fault address register (SCB_MMFAR) Address offset: 0x34 Reset value: undefined Required privilege: Privileged 4.4.13 Bus fault address register (SCB_BFAR) Address offset: 0x38 Reset value: undefined Required privilege: Privileged 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 MMFAR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 76 54 3 21 0 MMFAR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 MMFAR[31:0]: Memory management fault address When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the memory management fault. When an unaligned access faults, the address is the actual address that faulted. Because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. Flags in the MMFSR register indicate the cause of the fault, and whether the value in the MMFAR is valid. See Configurable fault status register (SCB_CFSR) on page 142. 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 BFAR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 76 54 3 21 0 BFAR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 BFAR[31:0]: Bus fault address When the BFARVALID bit of the BFSR is set to 1, this field holds the address of the location that generated the bus fault. When an unaligned access faults the address in the BFAR is the one requested by the instruction, even if it is not the address of the fault. Flags in the BFSR register indicate the cause of the fault, and whether the value in the BFAR is valid. See Configurable fault status register (SCB_CFSR) on page 142. |
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