UM0116

Read/program the STR7 embedded Flash

13/27

Bit 15

PWD: Power Down Mode (Read/Write).

When the microcontroller is put in a specific low power mode (see note below),

the Flash module can be put into two different low power modes.

0: Normal Mode (default), Flash Stand-by mode is selected (immediate read

from Flash is possible, but some residual power consumption is present).

1: The Flash module enters Power-Down mode. (recovery time of 20µs needed

before reading, but lower power consumption)

Note:

In the STR71x family the PWD bit acts only in STOP and LPWFI

modes. Whereas in the STR73x it acts only in LPWFI mode. For

further details, refer to the specific STR7 microcontroller reference

manual and datasheet, Power section.

Bit 14:5

Reserved, must be kept at reset value (0).

Bit 4

LOCK: Flash Register Access Locked (Read Only).

When this bit is set, it means that the access to all the Flash control registers is

locked: any read access to the registers will output invalid data (0xE6000010)

and any write access will be ineffective. Please note that the “1” of the invalid

data is located exactly in the position of the LOCK bit: therefore it is the only bit

the user can always access to detect the status of the Flash registers. The

LOCK bit is automatically set when the Flash bit WMS is set.

Once it is found low, the rest of FLASH_CR0 and all the other Flash registers

are user accessible.

Bit 3

Reserved, must be kept at reset value (0).

Bit 2:1

BSY[1:0]: Bank 1:0 Busy (Read Only).

These bits indicate that a write operation is ongoing in the corresponding bank.

They are automatically set when bit WMS is set. A Set Protection operation

sets bit BSY0. When these bits are set any read access to the corresponding

bank will output invalid data, while any write access to the bank will be ignored.

At the end of the write operation or during a Program or Erase Suspend these

bits are automatically reset and the bank returns to read mode. After a Program

or Erase Resume these bits are automatically set again. All BSY[1:0] bits

remain high for a maximum of 20

µs after Power-Up and when exiting Power-

Down mode, meaning that the Flash banks are not yet ready to be accessed.

Bit 0

Reserved, must be kept at reset value (0).