3

System modules

This section describes the system module peripherals (RST, CLK, System timers, PWR) bits and registers migration from revision

13 to revision 14 of the STM32W108xx datasheet.

3.1

Resets

For the RST IP, there are no updates in term for structure but the only updates are related to the bits and registers naming.

3.1.1

STM32W108xx RST bits and registers overview

Table 5 gives the list of the changes (renaming) made in the RST bits and registers.

Table 5.

RST bits and registers overview

STM32W108xx RST bits/registers naming overview

0X002C

RESET_

EVENT

Reserved

CPU_

LOCKUP

OPT_BYTE

_FAIL

WAKE_UP_

DSLEEP

SW_

RST

W_

DOG

RSTB_

PIN

POWER_

LV

POWER_

HV

RST_SR

LKUP

OBFAIL

WKUP

SWRST

WDG

PIN

PWRLV

PWRHV