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AN4325 Datasheet(PDF) 9 Page - STMicroelectronics |
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AN4325 Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 27 page ![]() DocID024966 Rev 1 9/27 AN4325 Power supplies and reset sources of the STM32F030 family 26 1.2 Reset and power supply supervisor 1.2.1 Power-on reset (POR) / power-down reset (PDR) The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits which are always active and ensure proper operation above a threshold of 2.4 V. The device remains in Reset mode when the monitored supply voltage is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The POR monitors only the VDD supply voltage. During the startup phase VDDA must arrive first and be greater than or equal to VDD. The PDR monitors both the VDD and VDDA supply voltages. However, the VDDA power supply supervisor can be disabled (by programming a dedicated option bit VDDA_MONITOR) to reduce the power consumption if the application design ensures that VDDA is higher than or equal to VDD. For more details on the power on / power down reset threshold, refer to the electrical characteristics section in the datasheet. Figure 3. Power on reset/power down reset waveform |
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