AN4365 datasheet(9/35 Pages) STMICROELECTRONICS

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AN4365

STM32F4 power consumption

1.2

Power-saving methods and features

In this part, we give a brief description of power-saving features that help a lot to reduce

current consumption and reach an optimal trade-off between performance processing and

power efficiency.

Note:

The majority of these features are common in all STM32F2 and STM32F4 MCUs, so the

user can get more details by referring to application note “How to achieve the lowest current

consumption with STM32F2xx” (AN3430) and to reference manuals RM0090 and RM0344.

1.2.1

System clock configuration and management

The clock controller in STM32F4 provides a high degree of flexibility with various clock

sources (external crystal HSE, internal oscillator HSI, phase-locked loop PLL, internal

oscillator LSI, external oscillator LSE), which are used to run the core and peripherals.

Dynamic power dissipation of CMOS logic is proportional to the operating frequency when

the operating voltage is fixed. The system over-clocking should be avoided by slowing the

system clock when the maximum rate is not needed.

The user should pay attention to the minimum system clock required by some peripherals

that need a specific clock like Ethernet, USB high speed and full speed, I2S and SDIO.

Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2)

and the low-speed APB (APB1) domains. To optimize power consumption, the user should

use the highest prescalers in order to provide just the needed clocks to peripherals and

avoid over-clocking that causes a consumption penalty. Power consumption can be further

lowered by gating clocks to the APBx and AHBx peripherals when they are not in use.

1.2.2

Dynamic voltage and frequency scaling

Dynamic current: I = P/V = C * V * f

So, reducing the operating voltage of the device is a useful step to reduce the overall power

consumption. Furthermore, many embedded systems do not require the system’s full

processing capabilities at all times because not all subsystems are always active. When this

is the case, the system can remain in the active mode without the processor running at its

maximum operating frequency. The voltage supplied to the processor can be lowered when

a lower frequency is sufficient. With such intelligent power management, we reduce the

power drawn from the battery by monitoring the processor input voltage in response to the

system’s performance requirements.

That consists in scaling the STM32F4 regulator output voltage that supplies the 1.2 V

domain (core, memories and digital peripherals) when we lower the clock frequency based

on processing needs.

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