LT1578CS8 datasheet(21/28 Pages) LINER

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LT1578/LT1578-2.5

APPLICATIONS INFORMATION

Analog experts will note that around 7kHz, phase dips

close to the zero phase margin line. This is typical of

switching regulators, especially those that operate over a

wide range of loads. This region of low phase is not a

problem as long as it does not occur near unity-gain. In

practice, the variability of output capacitor ESR tends to

dominate all other effects with respect to loop response.

Variations in ESR

will cause unity-gain to move around,

but at the same time phase moves with it so that adequate

phase margin is maintained over a very wide range of ESR

(

≥ ±3:1).

What About a Resistor in the Compensation Network?

It is common practice in switching regulator design to add

a “zero” to the error amplifier compensation to increase

loop phase margin. This zero is created in the external

network in the form of a resistor (RC) in series with the

compensation capacitor. Increasing the size of this resis-

tor generally creates better and better loop stability, but

there are two limitations on its value. First, the combina-

tion of output capacitor ESR and a large value for RC may

cause loop gain to stop rolling off altogether, creating a

gain margin problem. An approximate formula for RC

where gain margin falls to zero is:

R Loop

ESR

OUT

Gain = 1

()=()( )( )( )

121

GMP = Transconductance of power stage = 1.5A/V

GMA = Error amplifier transconductance = 1(10–3)

ESR = Output capacitor ESR

1.21 = Reference voltage

With VOUT = 5V and ESR = 0.1Ω, a value of 27.5k for RC

would yield zero gain margin, so this represents an upper

limit. There is a second limitation however which has

nothing to do with theoretical small signal dynamics. This

resistor sets high frequency gain of the error amplifier,

including the gain at the switching frequency. If the

switching frequency gain is high enough, an excessive

amout of output ripple voltage will appear at the VC pin

resulting in improper operation of the regulator. In a

marginal case,

subharmonic switching occurs, as

evidenced by alternating pulse widths seen at the switch

node. In more severe cases, the regulator squeals or

hisses audibly even though the output voltage is still

roughly correct. None of this will show on a Bode plot

since this is an amplitude insensitive measurement.

Tests

have shown that if ripple voltage on the VC is held to less

than 100mVP-P, the LT1578 will generally be well behaved.

The formula below will give an estimate of VC ripple

voltage when RC is added to the loop, assuming that RC is

large compared to the reactance of CC at 200kHz.

ESR

VL f

C RIPPLE

OUT

() = ()( )

−

()( )( )

121

GMA = Error amplifier transconductance (1000µMho)

If a series compensation resistor of 15k gave the best

overall loop response, with adequate gain margin, the

resulting VC pin ripple voltage with VIN = 10V, VOUT = 5V,

ESR = 0.1

Ω, L = 30µH, would be:

C RIPPLE

()

−

= ()()

−

()( )( )

()

()(

)

1 10

10 5 01 121

10 30 10

200 10

0 151

•.

••

This ripple voltage is high enough to possibly create

subharmonic switching. In most situations a compromise

value (< 10k in this case) for the resistor gives acceptable

phase margin and no subharmonic problems. In other

cases, the resistor may have to be larger to get acceptable

phase response, and some means must be used to control

ripple voltage at the VC pin. The suggested way to do this

is to add a capacitor (CF) in parallel with the RC/CC network

on the VC pin. The pole frequency for this capacitor is

typically set at one-fifth of the switching frequency so that

it provides significant attenuation of the switching ripple,

but does not add unacceptable phase shift at the loop

unity-gain frequency. With RC = 15k,

= ()( )( )= ()()=

200 10

265

•

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