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UPD75402ACT Datasheet(PDF) 16 Page - NEC |
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UPD75402ACT Datasheet(HTML) 16 Page - NEC |
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16 / 48 page ![]() 16 µPD75402A(A) 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit, which outputs clock pulses from pin P22/PCL, is used for supplying clock pulses for peripheral LSIs or for remote control output. • Clock output (PCL): 1.05 MHz, 524 kHz, 65.5 kHz (when fXX is 4.19 MHz). Fig. 5-2 shows the configuration of the clock output circuit. Fig. 5-2 Configuration of the Clock Output Circuit From the clock generator CLOM3 0 Selector Output buffer Port 2 input/ output mode specification bit P22 output latch P22/PCL Internal bus 4 Φ f XX/2 6 PORT2.2 Bit 2 of PMGB CLOM1 CLOM0 CLOM Remark The clock output circuit is designed not to output high-frequency pulses when clock output is switched between the enable and disable states. |
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