UPD75P0076 datasheet(7/62 Pages) NEC

7 / 62 page

µPD75P0076

3.2 Non-port Pins (1/2)

Pin name

I/O

Alternate function

Function

After

Circuit

reset

typeNote

TI0

P13

Inputs external event pulses to the timer/event

Input

<B>-C

TI1

P12/INT2

counter.

PTO0

P20

Timer/event counter output

Input

E-B

PTO1

P21

PCL

P22

Clock output

BUZ

P23

Optional frequency output (for buzzer output or

system clock trimming)

SCK

I/O

P01

Serial clock I/O

Input

<F>-A

SO/SB0

P02

Serial data output

<F>-B

Serial data bus I/O

SI/SB1

P03

Serial data input

<M>-C

Serial data bus I/O

INT4

P00

Edge detection vectored interrupt input (both rising

<B>

edge and falling edge detection)

INT0

P10

Edge detection vectored

Noise eliminator/

Input

<B>-C

interrupt input (detection

asynchronous selection

INT1

P11

edge can be selected).

Asynchronous

INT0/P10 can select a noise

eliminator.

INT2

P12/TI1

Rising edge detection

Asynchronous

testable input

KR0 to KR3

P60/AN4 to

Falling edge detection testable input

Input

<Y>-D

P63/AN7

AN0 to AN3

P110 to P113

Analog signal input

Input

Y-A

AN4 to AN7

P60/KR0 to

<Y>-D

P63/KR3

AVREF

—

A/D converter reference voltage

—

Z-N

AVSS

—

A/D converter reference GND potential

—

Z-N

—

Crystal/ceramic connection pin for the main system

—

clock oscillator. When inputting the external clock,

input the external clock to pin X1, and the inverted

phase of the external clock to pin X2.

XT1

—

Crystal connection pin for the subsystem clock

—

XT2

—

oscillator. When the external clock is used, input the

external clock to pin XT1, and the inverted phase of

the external clock to pin XT2. Pin XT1 can be used

as a 1-bit input (test) pin.

RESET

—

System reset input (low-level active)

—

<B>

Note

Circuit types enclosed in brackets indicate Schmitt triggered inputs.

UPD75P0076 Datasheet(PDF) 7 Page - NEC

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