LTC1325CSW datasheet(18/24 Pages) LINER

18 / 24 page

LTC1325

APPLICATIONS INFORMATION

between the VBAT and Sense pins and the internal

divider should be set to divide-by-1.

The minimum VDD supply must be greater than the

end-of-charge voltage VEC times the number of cells

(n) in the battery plus drops across the on-resistance

of the PFET, inductor (VL), battery internal resistance

RINT and sense resistor RSENSE.

Minimum VDD should be the greater voltage of the

results from these two equations:

Min VDD =ICHRG[RDS(ON)(P1) + RSENSE +

n(RINT)] + n(VEC) + VL

or,

Min VDD = n(VEC) + 1.8V

Assuming VEC = 1.6V, the LTC1325 will charge up to

8 cells with a 16V supply. For a higher number of cells,

an external level shifter and regulator are needed.

In some applications, there are other circuits attached

to the charging supply. When the charging supply

(VDC) is powered down or removed, the battery may

supply current to these circuits through the PFET body

diode. To prevent this, a blocking diode can be added

in series with VDC as shown in the circuit in the Typical

Application section.

3. Inductor L: To minimize losses, the inductor should

have low winding resistance. It should be able to

handle expected peak charging currents without satu-

ration. If the inductor saturates, the charging current

is limited only by the total PFET RDS(ON), inductor

winding resistance, RSENSE and VDD source resis-

tance. This fault current may be high enough to

damage the battery or cause the maximum power

ratings of the PFET, inductor or RSENSE to be ex-

ceeded.

4. Catch Diode D1: The catch diode should have a low

forward drop and fast reverse recovery time to mini-

mize power dissipation. Total power loss is given by:

PdD1 = VF(IF) + (VR)(f)(tRR)(IF′)

The LTC1325 has five duty ratio and four VDAC settings

giving 20 possible charge rates (for a given value of

RSENSE) as shown in the following table. For any

combination of VDAC and duty ratio, the average

charging current is given by:

AVG ICHRG = VDAC(Duty Ratio)/RSENSE

NORMALIZED

DUTY RATIO

VDAC

1/2

1/4

1/8

1/16

1(VR1 = 1, VR0 = 1)

1/2

1/4

1/8

1/16

1/3(VR1 = 1, VR0 = 0)

1/3

1/6

1/12

1/24 1/48

1/5(VR1 = 0, VR0 = 1)

1/5

1/10

l/20

1/40 1/80

1/10(VR1 = 0, VR0 = 0) 1/10

1/20

1/40

1/80 1/160

Note that the table entries give relative charge rates

assuming that the VR1 = 1, VR0 = 1, duty ratio = 1 entry

is equivalent to a 1C charge rate. Therefore, the charge

rate (in C-units) for other VR1, VR0, and duty ratio

settings may be read directly from the table. In gen-

eral, the VR1 = 1, VR0 = 1, duty ratio = 1 entry can be

equivalent to any charge rate, say k times 1C. Then all

entries in the table should be multiplied by k. In

general, VDAC and duty ratio settings are changed by

the microprocessor to charge batteries of different

capacities or to alter charge rates when charging the

same battery in several stages. For best accuracy, VR1

and VR0 should be set to 1 where possible.

The power dissipation of the sense resistor varies

between charge, discharge and gas gauge modes and

should be calculated for all three modes. Typically,

dissipation is higher in discharge and gas gauge

modes since batteries can deliver higher currents than

they can be charged with.

In gas gauge mode, the load current supplied by the

battery should not exceed 450mV/RSENSE for the gas

gauge to remain linear in response. RSENSE should be

low enough to ensure that ILOAD(RSENSE) does not

fall below ground by more than 1 diode drop.

2. VDD Supply: VDD should be at least 1.8V above the

maximum battery voltage to prevent a BATP = 0 error

when the LTC1325 is in charge or discharge mode. If

this requirement cannot be met in a specific applica-

tion, an external battery divider should be connected

LTC1325CSW Datasheet(PDF) 18 Page - Linear Technology

LTC1325CSW Datasheet(HTML) 18 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL