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UPD75P068CU Datasheet(PDF) 21 Page - NEC

Part # UPD75P068CU
Description  4 BIT SINGLE-CHIP MICROCOMPUTER
PDF  40 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD75P068CU Datasheet(HTML) 21 Page - NEC

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µPD75P068
tKCY3
tKL3
tKH3
tSIK3
tKSI3
tKSO3
tKSB
tSBK
tSBL
tSBH
SBI mode (SCK ... Internal clock output (master)):
SBI mode (SCK ... External clock input (slave)):
Note RL and CL are the resistance and capacitance of the SB0/SB1 output line load respectively.
250
1000
1600
3800
tKCY3/2 - 50
tKCY3/2 - 150
150
tKCY3/2
0
0
tKCY3
tKCY3
tKCY3
tKCY3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
RL = 1 k
Ω,
CL = 100 pFNote
Conditions
Parameter
Min.
Typ.
Max.
Unit
SCK cycle time
SCK high/low level
width
SB0/SB1 setup time
(referred to SCK
↑)
SB0/SB1 hold time
(referred to SCK
↑)
Delay time from SCK
↓
to SB0/SB1 output
From SCK
↑ to SB0/SB1↓
From SB0/SB1
↓ to SCK
SB0/SB1 low level width
SB0/SB1 high level
width
Symbol
Parameter
tKCY4
tKL4
tKH4
tSIK4
tKSI4
tKSO4
tKSB
tSBK
tSBL
tSBH
300
1000
Min.
Unit
Max.
Typ.
Conditions
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
RL = 1 k
Ω,
CL = 100 pFNote
VDD = 4.5 to 6.0 V
800
3200
400
1600
100
tKCY4/2
0
0
tKCY4
tKCY4
tKCY4
tKCY4
SCK cycle time
SCK high/low level
width
SB0/SB1 setup time
(referred to SCK
↑)
SB0/SB1 hold time
(referred to SCK
↑)
Delay time from SCK
↓
to SB0/SB1 output
From SCK
↑ to SB0/SB1↓
From SB0/SB1
↓ to
SCK
↓
SB0/SB1 low level width
SB0/SB1 high level
width
Symbol
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns



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