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LTC2483

2483fc

In addition to this gain error, the converter INL per-

formance is degraded by the reference source imped-

ance. The INL is caused by the input dependent terms

–VIN2/(VREF • REQ) – (0.5 • VREF • DT)/REQ in the reference

pin current as expressed in Figure 7. When using internal

oscillator, every 100Ω of reference source resistance

translates into about 0.61ppm additional INL error. When

CA0/F0 is driven by an external oscillator with a frequency

fEOSC, every 100Ω of source resistance driving REF+ or

REF– translates into about 2.18 • 10–6 • fEOSCppm ad-

ditional INL error. Figure 15 shows the typical INL error

due to the source resistance driving the REF+ or REF– pins

when large CREF values are used. The user is advised to

minimize the source impedance driving the REF+ and

REF– pins.

In applications where the reference and input common

mode voltages are different, extra errors are introduced.

For every 1V of the reference and input common mode

voltage difference (VREFCM – VINCM) and a 5V reference,

each ohm of reference source resistance introduces an

extra (VREFCM – VINCM)/(VREF • REQ) full-scale gain error,

which is 0.067ppm when using internal oscillator. If an

applicaTions inFormaTion

external clock is used, the corresponding extra gain error

is 0.24 • 10–6 • fEOSCppm.

The magnitude of the dynamic reference current depends

uponthesizeoftheverystableinternalsamplingcapacitors

andupontheaccuracyoftheconvertersamplingclock.The

accuracy of the internal clock over the entire temperature

andpowersupplyrangeistypicallybetterthan0.5%.Such

a specification can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/°C) are

used for the external source impedance seen by REF+

and REF–, the expected drift of the dynamic current gain

error will be insignificant (about 1% of its value over the

entire temperature and voltage range). Even for the most

stringent applications a one-time calibration operation

may be sufficient.

In addition to the reference sampling charge, the refer-

ence pins ESD protection diodes have a temperature de-

pendent leakage current. This leakage current, nominally

1nA (±10nA max), results in a small gain error. A 100Ω

source resistance will create a 0.05µV typical and 0.5µV

maximum full-scale error.

Figure 15. INL vs Differential Input Voltage and

Reference Source Resistance for CREF > 1µF

VIN/VREF (V)

–0.5

0.3

2483 F15

–2

–6

–4

–8

–10

–0.3

–0.1

0.1

0.5

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

TA = 25°C

CREF = 10µF

R = 1k

R = 100

R = 500

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