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UPD75P308 Datasheet(PDF) 21 Page - NEC |
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UPD75P308 Datasheet(HTML) 21 Page - NEC |
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21 / 34 page ![]() µPD75P308 21 1600 ns tKCY/2 -50 150 ns tKCY/2 ns 0 250 ns tKCY ns tKCY ns tKCY ns tKCY ns SCK Cycle Time SCK High-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0, 1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width SBI MODE (SCK: internal clock output (master)) Parameter Symbol Conditions MIN. TYP. MAX. Unit tKCY3 tKL3 tKH3 tSIK3 tKSI3 tKSO3 tKSB tSBK tSBL tSBH *: RL and CL are load resistance and load capacitance of the SO output line. SBI MODE (SCK: external clock output (master)) *: RL and CL are load resistance and load capacitance of the SO output line. ↑ ↑ RL = 1k Ω, CL = 100pF* ↓ → ↑ → ↓ ↓ → ↓ SCK Cycle Time SCK High-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0, 1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width Parameter Symbol Conditions MIN. TYP. MAX. Unit 1600 ns 100 ns tKCY/2 ns 0 300 ns tKCY ns tKCY ns tKCY ns tKCY ns tKCY4 tKL4 tKH4 tSIK4 tKSI4 tKSO4 tKSB tSBK tSBL tSBH ↑ ↑ RL = 1k Ω, CL = 100pF* ↓ → ↑ → ↓ ↓ → ↓ 5 5 ns 400 ns |
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