LTC1665IGN datasheet(10/16 Pages) LINER

10 / 16 page

LTC1665/LTC1660

OPERATIO

Table 2. DAC Address/Control Functions

ADDRESS/CONTROL

DAC STATUS

SLEEP STATUS

0000

No Change

Wake

0001

Load DAC A

Wake

0010

Load DAC B

Wake

0011

Load DAC C

Wake

0100

Load DAC D

Wake

0101

Load DAC E

Wake

0110

Load DAC F

Wake

0111

Load DAC G

Wake

1000

Load DAC H

Wake

1001

No Change

Wake

1010

No Change

Wake

1011

No Change

Wake

1100

No Change

Wake

1101

No Change

Wake

1110

No Change

Sleep

1111

Load ALL DACs

Wake

with Same

8/10-Bit Code

state and all DAC settings are retained in memory so that

when Sleep mode is exited, the outputs of DACs not

updated by the Wake command are restored to their last

active state.

Sleep mode is initiated by performing a load sequence to

address 1110b (the DAC input word D7-D0 [D9-D0] is

ignored). Once in Sleep mode, a load sequence to any

other address (including “No Change” addresses 0000b

and 1001-1101b) causes the LTC1665/LTC1660 to Wake.

It is possible to keep one or more chips of a daisy chain in

continuous Sleep mode by giving the Sleep instruction to

these chips each time the active chips in the chain are

updated.

Voltage Outputs

Each of the eight rail-to-rail output amplifiers contained in

these parts can source or sink up to 5mA. The outputs

swing to within a few millivolts of either supply rail when

unloaded and have an equivalent output resistance of 85

Ω

when driving a load to the rails. The output amplifiers are

stable driving capacitive loads up to 1000pF.

A small resistor placed in series with the output can be

used to achieve stability for any load capacitance. A 1

µF

load can be successfully driven by inserting a 20

Ω resis-

tor; a 2.2

µF load needs only a 10Ω resistor. In either case,

larger values of resistance, capacitance or both may be

safely substituted for the values given.

Rail-to-Rail Output Considerations

In any rail-to-rail output voltage DAC, the output is limited

to voltages within the supply range.

If the DAC offset is negative, the output for the lowest

codes limits at 0V as shown in Figure 3b.

Similarly, limiting can occur near full scale when the REF

pin is tied to VCC. If VREF = VCC and the DAC full-scale error

(FSE) is positive, the output for the highest codes limits at

VCC as shown in Figure 3c. No full-scale limiting can occur

if VREF is less than VCC – FSE.

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting can

occur.

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